Summary: Seeking engineers for the Hardware Security Test Team to validate and deploy information stored in OTP ROM/Fuses of chips for security, configuration, and yield improvement. Highlights: 1. Work on leading edge technology chips in a fast-paced environment 2. Develop and implement comprehensive security test plans and methodologies 3. Innovate and collaborate with a global team to excel Hardware Security Test Team is looking for engineers to work on leading edge technology chips. Our mission is to scrutinize, accurately validate, and deploy into mass production the information stored in the OTP (one time programmable) ROM or “Fuses” of our chips for the purposes of identification, security, product configuration, calibration, and yield improvement. **Responsibilities** -------------------- * Work closely with design teams and more experienced engineers to integrate OTP programming requirements into the overall product design. * Support the development and implementation of OTP programming strategies for tracking, provisioning, and configuring or SKU\-ing devices via Crypto Manager (CM) and Trust Management Engine (TME) cores. * Support the development and implementation of comprehensive security test plans and methodologies for ASIC, SOC, and multi\-chiplet devices. * Work in a fast\-paced environment to bring up silicon solutions for both internal and external customers. * Work on ATE (93K and UF\+) platforms to develop test programs in Java and VB that are scalable and tested extensively before deploying to production. * Preparing the test program for mass production by optimizing yield and throughput. * Develop validation procedures and leverage validation solutions and tools to ensure the integrity and correctness of the data stored in devices. * Support debug efforts to solve chip fusing functionality and yield issues. * Validate custom digital circuitry to support on\-board boot and other product\-specific security requirements. Must be able to support planning and execution of an ATE test program from start to finish, on time, under a tight test time budget, while also innovating to help our global team excel. Must work well in a team environment but also be self\-driven to complete tasks without supervision. Fusing is a destructive process, so attention to detail is a must. **Preferred Qualifications** ---------------------------- * English fluent (\>95% verbal and written). * Familiarity with basic test protocols such as TIC and JTAG. * Embedded SW development / FPGA programming is a plus. * Experience with SW/HW debug tools. Experience with Lauterbach Trace32 preferred. * Experience with SVN/GIT or other version control solutions. * Experience with PCB schematic capture and layout. * Experience with digital circuit design. **Minimum Qualifications** -------------------------- * BS. B. Eng. in Computer Engineering, Computer Science, Electrical Engineering, or related fields. * Attention to detail. * Experienced in Object Oriented Programming (OOP) languages (Java, C\+\+). Able to write Java code for basic ATE functionality/measurements. * Proficient with Unix/Linux. Scripting experience with Perl/Python preferred. * Strong verbal communication skills, ability to collaborate with many teams to gather requirements and debug issues. **Keywords** ------------ * One\-time programming (OTP), Fuses, Python, Scripting, OOP, Embedded SW, C/C\+\+, Java, Linux, Hardware Security, SW development, Databases, Computer Architecture, Digital Design.