Timing and Technology Engineer

Description

Summary: This role involves designing innovative SOC products at the block/IP-level and system-level for advanced semiconductor development. Highlights: 1. Work with best-in-class methodologies, tools, and technology 2. Drive STA methodology for the company using advanced tools 3. Contribute to timing convergence, design PPA, and advanced process technologies This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the market. Its silicon engineering drives solutions that deliver high performance, energy efficiency, and intelligent integration, complemented by a key role in advancing modern telecommunications through next\-generation wireless connectivity technologies. Its solutions are integrated into billions of devices worldwide, offering an ideal professional environment for talent seeking technological impact, innovation, and growth within a global context. The candidate will work with best\-in\-class methodologies, tools and technology to design innovative SOC products at the block/IP\-level and at system\-level in 5nm, 4nm and beyond (process technologies). * You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation. * Responsible for Spice simulations (Hspice/Primesim/Finesim/AFS/Spectre) for PVT corners validation and STA vs spice correlation. Timing package validation across advanced process technologies using PT/PT\-SI and Tempus. * You will facilitate and drive STA methodology for the company using PT\-SI, Tempus and best in class timing ECO tools. Work on timing sign off specification for different projects and support timing sign off for complex SOC’s. Hands on contribution for STA timing sign off. * A timing Engineer should be able to understand all kind of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC/DCT/DCG/FC/Genus/Oasis, ICC2/FusionCompiler/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus. * You should have good execution knowledge. * Your contribution should improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring\-up from PDK to VLSI design production. * You should have good programming skills Python, Perl, TCL, Unix shell, C/C\+\+. * ML modeling experience is a plus.