Summary: This Senior Engineer role involves developing ATE test solutions and characterizing high-speed I/O interfaces for advanced SoCs within a global leader in semiconductor design. Highlights: 1. Work with a global leader company in advanced semiconductors. 2. Develop manufacturing test solutions for HSIO/SERDES PHYs on ATE platforms. 3. Lead first-silicon bring-up, electrical characterization, and debug. This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the market. Its silicon engineering drives solutions that deliver high performance, energy efficiency, and intelligent integration, complemented by a key role in advancing modern telecommunications through next\-generation wireless connectivity technologies. Its solutions are integrated into billions of devices worldwide, offering an ideal professional environment for talent seeking technological impact, innovation, and growth within a global context. **Senior HSIO ATE Test Development \& Characterization Engineer** We are looking for a Senior Engineer to join our Post‑Silicon Engineering team. In this role, you’ll develop ATE test solutions and characterize high‑speed I/O (HSIO) interfaces for advanced SoCs. You’ll work on SERDES‑based PHYs, help define test methodologies, and drive first‑silicon debug on cutting‑edge technologies. This position is hands‑on and highly collaborative, involving cross‑functional work with design, systems, process, and product engineering teams around the world. **What You’ll Do** ------------------ * Develop **manufacturing test solutions** for HSIO/SERDES PHYs (PCIe, USB3, UFS, DP, MIPI DSI/CSI, etc.) on ATE platforms. * Create **test and characterization plans**, including DFT requirements and test hardware needs. * Write and debug **ATE programs, routines, and automation** to execute test plans. * Lead **first‑silicon bring‑up**, electrical characterization, and debug across multiple operating corners. * Analyze **parametric data**, test results, and high‑volume yield trends to drive improvements in quality, yield, and test time. * Support **failure analysis** and work closely with engineering teams to root‑cause and resolve issues. * Stay up to date on new technologies, industry trends, and competitor approaches. **Minimum Qualifications** -------------------------- * Bachelor’s degree in Engineering, Computer Science, or a related technical field. **Preferred Qualifications** ---------------------------- * Master’s degree in Electrical/Computer Engineering or related field. * **3–5 years of experience in hardware, post‑silicon validation, or test development.** * Solid understanding of **VLSI**, **CMOS**, and **mixed‑signal** fundamentals. * Experience with **HSIO/SERDES characterization or validation** (PCIe, USB2/3/4, UFS, MIPI CSI/DSI, etc.) is a strong plus. * Good **ASIC characterization** skills; system‑level understanding is helpful. * Familiarity with **Advantest 93K** ATE platform is a plus. * Knowledge of **signal integrity** concepts. * Programming experience (C/C\+\+/Java/Perl) and exposure to **test automation/scripting**. * Strong problem‑solving, debug, communication, and documentation skills. * Able to work independently, manage priorities, and drive issues to closure.